1. Field of the Invention
The present invention relates to a non-volatile memory, and more particularly to a composite non-volatile memory including a ferroelectric capacitor and an MFS (metal-ferroelectric-semiconductor) field effect transistor, MFIS (metal-ferroelectric-insulator-semiconductor) field effect transistor or MFMIS (metal-ferroelectric-insulator-semiconductor) field effect transistor.
2. Description of the Related Art
The ferroelectric memory which is being researched nowadays is roughly classified into two systems. The one is a memory of a system in which the quantity of inverted charges of a ferroelectric capacitor is detected. This system includes a ferroelectric capacitor and a select transistor.
The other is a memory of the system in which a change in the resistance of semiconductor due to spontaneous polarization of ferroelectric is detected. A representative system thereof is an MFSFET. This MFSFET has a MIS structure using ferroelectric for a gate insulating film. In this structure, a ferroelectric layer must be directly formed on a semiconductor surface so that it is difficult to control the interface between the ferroelectric and semiconductor (ferroelectric/semiconductor interface). Therefore, it has been said that it is difficult to manufacture a good memory using this MFSFET. For this reason, at present, the main tendency is the memory structure in which a buffer layer is formed on the ferroelectric/semiconductor interface. However, we have proposed an FET of a MFMIS structure, as seen from an equivalent circuit diagram of FIG. 6 and a sectional view of FIG. 7, in which a buffer layer composed of a metallic layer (M) and an insulating layer (I) is formed on the ferroelectric/semiconductor interface. This FET having MFMIS structure has a gate oxide film 5, floating gate 6, ferroelectric film 7 and control gate 8 which are successively stacked on a channel region formed between source/drain regions 2 and 3 of a semiconductor substrate 1.
In this configuration, when a positive voltage is applied to the control gate 8 over the substrate 1, the ferroelectric film 7 generates inverted polarization. Even when the application of the voltage to the control gate 8 is ceased, a negative charge is generated on the channel region CH owing to the residual polarization of the ferroelectric film 7. This state is referred to as the state of "1".
Reverse to the above case, when a negative voltage is applied to the control gate 8, the ferroelectric film 8 generates the inverted polarization in an opposite direction that in the above case. Even when the application of the voltage to the control gate 8, a positive charge is generated to the channel region CH owing to the residual polarization of the ferroelectric film 7. This state is referred to as the state of "0". In this way, the information of "1" or "0" can be written in the FET.
The read of the written information is executed by applying a read voltage V.sub.r to the control gate 8. The read voltage V.sub.r is prescribed between the threshold value V.sub.th1 in the state of "1" and the threshold value V.sub.th0 in the state of "0". It can be decided whether the written information is "1" or "0" by detecting whether or not the drain current has flowed when the read voltage Vr is applied to the control gate 8.
In this way, the FET of the MIS structure permits a single memory cell to be formed by a single element so that non-destructive read can be made satisfactorily. The former ferroelectric memory including a select transistor and a ferroelectric capacitor, as seen from an equivalent circuit diagram of FIG. 8 and a sectional view of FIG. 9, can hold charges of two values of "0" and "1" in a single ferroelectric capacitor. For example, as understood from the hysteresis characteristic as shown in FIG. 10, where the storage information of "0" is written, with the voltage applied to the capacitor being minus (with a select transistor T.sub.SW being on, a minus potential is applied to a bit line BL and a plus potential is applied to a plate line PL) after having passed point d, the applied voltage is restored to zero. In this case, the polarized value results in a residual polarized point a so that the storage information of "0" can be written. On the other hand, where storage information of "1" is written, with the voltage applied to the capacitor being plus, after having passed point b, the applied voltage is restored to zero. In this case, the polarized value results in a residual polarized point c so that the storage information of "1" can be written.
The read of data can be carried out in such a manner that the quantity of charges flowing into the bit line when the voltage is applied to the capacitor is detected.
The charges flowing from the ferroelectric capacitor into the bit line changes the potential on the bit line. The bit line has a parasitic bit line capacitance Cb generated because of the presence of the bit line itself. When the select transistor is turned on to select the memory to be read, according to the information stored in each selected memory cell, the charge is outputted onto the bit line. The value obtained when this charge is divided by the entire capacitance of the bit line represents the potential on the bit line.
A difference between the bit line potentials is read in comparison with a predetermined reference potential.